Power architecture - Qualcomm Dragonwing Documentation

The CPU subsystem architecture describes the organization of CPU cores and their power domains. Understanding the architecture helps you to monitor the CPU core usage and balance the power consumption and performance of the device.

APSS is a set of CPUs organized into clusters. All CPU cores in a cluster operate at a similar frequency. Each CPU core in a cluster has a dedicated L1 and L2 cache.The CPU subsystem consists of three clusters and L3 cache as follows:

Qualcomm^® Kryo^™ CPU Prime cluster, which has a performance CPU core
Kryo Gold cluster, which has CPU cores with balanced power and performance
Kryo Silver cluster, which has low power CPU cores for lightweight applications
Common L3 cache

Figure : QCS6490/QCS5430 APSS CPU subsystem architecture

The CPU subsystem operates on two power domains, each supplied by a dedicated switched mode power supply (SMPS) rail. The following are the supported power domains:

Table : Power domains and their descriptions
Power domains Description
VDD_APC0 Power domain for the Silver cluster CPU cores and L3 cache digital circuit
VDD_APC1 Power domain for the Gold and Prime clusters CPU cores
Chip_MX Power domain for the L1, L2, and L3 cache memories
Note To know more about CPU core arrangement, see QCS6490 Data Sheet and QCS5430 Data Sheet.

	Table : Power domains and their descriptions
Power domains	Description
`VDD_APC0`	Power domain for the Silver cluster CPU cores and L3 cache digital circuit
`VDD_APC1`	Power domain for the Gold and Prime clusters CPU cores
`Chip_MX`	Power domain for the L1, L2, and L3 cache memories

The CPU subsystem consists of two clusters with a dedicated L3 cache for each cluster. Each CPU core in a cluster has a dedicated L1 and L2 cache. All CPU cores in a cluster operate at a similar frequency.

Figure : IQ-9075 APSS CPU subsystem architecture

The CPU subsystem operates on two power domains, each supplied by a dedicated SMPS rail. The following are the supported power domains:

Table : Power domains and their descriptions

Power domains	Description
`VDD_APC0`	Power domain for Cluster0 CPU cores and L3 cache digital circuit
`VDD_APC1`	Power domain for Cluster1 CPU cores and L3 cache digital circuit
`Chip_MX`	Power domain for the L1, L2, and L3 cache memories

To know more about CPU core arrangement, see IQ-9075 Data Sheet.

APSS is a set of CPUs organized into clusters. All CPU cores in a cluster operate at a similar frequency. Each CPU core in a cluster has a dedicated L1 and L2 cache. The CPU subsystem consists of three clusters and L3 cache as follows:

Kryo Prime cluster with performance CPU cores

Kryo Gold cluster, which has CPU cores with balanced power and performance

Kryo Silver cluster, which has low power CPU cores for lightweight applications

Silver cluster has a dedicated L3 cache

Gold and Prime clusters share a dedicated L3 cache

Figure : IQ-8275 APSS CPU subsystem architecture

The CPU subsystem operates on two power domains, each supplied by a dedicated SMPS rail. The following are the supported power domains:
Table : Power domains and their descriptions
Power domains Description
VDD_APC0 Power domain for the Gold and Prime cluster CPU cores and L3 cache digital circuit
VDD_APC1 Power domain for the Silver cluster CPU cores and L3 cache digital circuit
Chip_MX Power domain for the L1, L2, and L3 cache memories

	Table : Power domains and their descriptions
Power domains	Description
`VDD_APC0`	Power domain for the Gold and Prime cluster CPU cores and L3 cache digital circuit
`VDD_APC1`	Power domain for the Silver cluster CPU cores and L3 cache digital circuit
`Chip_MX`	Power domain for the L1, L2, and L3 cache memories

To know more about CPU core arrangement, see IQ-8275 Data Sheet.

APSS is a set of CPUs organized into clusters. All CPU cores in a cluster operate at a similar frequency. Each CPU core in a cluster has a dedicated L1 and L2 cache.

The CPU subsystem consists of two clusters and L3 cache as follows:

Qualcomm^® Kryo^™ Gold cluster, which has CPU cores with balanced power and performance
Kryo Silver cluster, which has low power CPU cores for lightweight applications
Common L3 cache

Figure : IQ-615 APSS CPU subsystem architecture

The CPU subsystem operates on two power domains, each supplied by a dedicated SMPS rail. The following are the supported power domains:
Table : Power domains and their descriptions
Power domains Description
VDD_APC0 Power domain for the Silver cluster CPU cores and L3 cache digital circuit
VDD_APC1 Power domain for the Gold cluster CPU cores
Chip_MX Power domain for the L1, L2, and L3 cache memories

	Table : Power domains and their descriptions
Power domains	Description
`VDD_APC0`	Power domain for the Silver cluster CPU cores and L3 cache digital circuit
`VDD_APC1`	Power domain for the Gold cluster CPU cores
`Chip_MX`	Power domain for the L1, L2, and L3 cache memories

To know more about CPU core arrangement, see IQ-615 Data Sheet.

APSS is a set of CPUs organized into clusters. All CPU cores in a cluster operate at a similar frequency. Each CPU core in a cluster has a dedicated L1 cache and each cluster has a dedicated L2 cache.

The CPU subsystem is organized into three clusters, each with its own dedicated L2 cache:

NCC Efficiency Cluster 0, which has 4 Qualcomm Oryon^™ CPU efficiency cores for lightweight applications
NCC Performance Cluster 1, which has 4 Oryon Performance CPU cores for balanced power and performance workloads
NCC Performance Cluster 2, which has 4 Oryon Performance CPU cores for balanced power and performance workloads
Shared L2 cache per each cluster

Figure : IQ-X7181 APSS CPU subsystem architecture

The CPU subsystem uses separate logic and memory power domains for each cluster. Each domain is powered by its own dedicated SMPS rail. Following are the supported power domains:
Table : Power domains and their descriptions
Power domains Description
VDD_CLUSTER0_CX Logic power domain for the NCC Efficiency cluster 0 CPU cores
VDD_CLUSTER0_MX Memory power domain for the NCC Efficiency cluster 0 L1 and L2 caches
VDD_CLUSTER1_CX Logic power domain for the NCC Performance cluster 1 CPU cores
VDD_CLUSTER1_MX Memory power domain for the NCC Performance cluster 1 L1 and L2 caches
VDD_CLUSTER2_CX Logic power domain for the NCC Performance cluster 2 CPU cores
VDD_CLUSTER2_MX Memory power domain for the NCC Performance cluster 2 L1 and L2 caches

	Table : Power domains and their descriptions
Power domains	Description
`VDD_CLUSTER0_CX`	Logic power domain for the NCC Efficiency cluster 0 CPU cores
`VDD_CLUSTER0_MX`	Memory power domain for the NCC Efficiency cluster 0 L1 and L2 caches
`VDD_CLUSTER1_CX`	Logic power domain for the NCC Performance cluster 1 CPU cores
`VDD_CLUSTER1_MX`	Memory power domain for the NCC Performance cluster 1 L1 and L2 caches
`VDD_CLUSTER2_CX`	Logic power domain for the NCC Performance cluster 2 CPU cores
`VDD_CLUSTER2_MX`	Memory power domain for the NCC Performance cluster 2 L1 and L2 caches

APSS is a set of CPUs organized into clusters. All CPU cores in a cluster operate at a similar frequency. Each CPU core in a cluster has a dedicated L1 cache and each cluster has a dedicated L2 cache.

The CPU subsystem consists of two clusters and a dedicated L2 cache as follows:

NCC Performance Cluster 0, which has 4 Qualcomm Oryon Performance CPU cores for balanced power and performance workloads
NCC Performance Cluster 1, which has 4 Qualcomm Oryon Performance CPU cores for balanced power and performance workloads
Shared L2 cache per each cluster

Figure : IQ-X5121 APSS CPU subsystem architecture

The CPU subsystem operates on dedicated logic and memory power domains for each cluster. Each domain is powered by its own dedicated SMPS rail. Following are the supported power domains:
Table : Power domains and their descriptions
Power domains Description
VDD_CLUSTER0_CX Logic power domain for the NCC Performance cluster 0 CPU cores
VDD_CLUSTER0_MX Memory power domain for the NCC Performance cluster 0 L1 and L2 caches
VDD_CLUSTER1_CX Logic power domain for the NCC Performance cluster 1 CPU cores
VDD_CLUSTER1_MX Memory power domain for the NCC Performance cluster 1 L1 and L2 caches

	Table : Power domains and their descriptions
Power domains	Description
`VDD_CLUSTER0_CX`	Logic power domain for the NCC Performance cluster 0 CPU cores
`VDD_CLUSTER0_MX`	Memory power domain for the NCC Performance cluster 0 L1 and L2 caches
`VDD_CLUSTER1_CX`	Logic power domain for the NCC Performance cluster 1 CPU cores
`VDD_CLUSTER1_MX`	Memory power domain for the NCC Performance cluster 1 L1 and L2 caches

APSS is a set of CPUs organized into clusters. All CPU cores in a cluster operate at a similar frequency.

The CPU subsystem consists of a single cluster and a common L3 cache:

1 Cortex-A78c CPU core with dedicated L1 and L2 caches for balanced power and performance workloads
Common L3 cache

Figure : CQ-2390 APSS CPU subsystem architecture

The CPU subsystem operates on one power domain supplied by a dedicated SMPS rail. Following are the supported power domains:
Table : Power domains and their descriptions
Power domains Description
VDD_APC0 Power domain for the Cortex-A55 and Cortex-A78c CPU cores and L3 cache digital circuit
Chip_MX Power domain for the L1, L2, and L3 cache memories