Overview - Qualcomm Dragonwing Documentation

This guide describes the low-speed and high-speed I/O peripheral interface subsystems used in the Qualcomm Dragonwing IQ-9075 SoC. Low-speed interfaces (via QUP v3 serial engine):

UART, SPI, I2C, I3C

High-speed interfaces:

PCIe, USB

IQ-9075 Interface Overview

2× QUP v3 Serial Engine	QUP0_V3	QUP1_V3	QUP2_V3
Application processor serial engine instances	7	7	1

3× USB Controller	0xa600000	0xa800000	0xa400000
Maximum speed	USB 3.x SuperSpeed	USB 3.x SuperSpeed	USB 2.0 High Speed

2× PCIe Controller	RC1	RC0
Speed	Gen4 2L (8 GT/s)	Gen4 4L (8 GT/s)
Config space	0x40100000 (1 MB)	0x60100000 (1 MB)
BAR space	0x40300000 (509 MB)	0x60300000 (509 MB)
Power management	ASPM (L1/L1ss, L0s)	ASPM (L1/L1ss, L0s)

QUP v3 Protocol and GPIO Mapping

QUP0 (SE0–SE5)

QUP_SE (addr)	SPI-M	I2C-M	UART	HS UART	GPIO mapping
qup0_se0 (0x980000)	spi0	i2c0	uart0	—	20, 21, 22, 23
qup0_se1 (0x984000)	spi1	i2c1	uart1	—	24, 25, 26, 27
qup0_se2 (0x988000)	spi2	i2c2	uart2	uart2	36, 37, 38, 39
qup0_se3 (0x98c000)	spi3	i2c3	uart3	uart3	28, 29, 30, 31
qup0_se4 (0x990000)	spi4	i2c4	uart4	—	32, 33, 34, 35
qup0_se5 (0x994000)	spi5	i2c5	uart5	—	36, 37, 38, 39

QUP1 (SE0–SE6)

QUP_SE (addr)	SPI-M	I2C-M	UART	HS UART	GPIO mapping
qup1_se0 (0xa80000)	spi7	i2c7	uart7	—	40, 41, 42, 43
qup1_se1 (0xa84000)	spi8	i2c8	uart8	—	42, 43, 40, 41
qup1_se2 (0xa88000)	spi9	i2c9	uart9	uart9	46, 47, 44, 45
qup1_se3 (0xa8c000)	spi10	i2c10	uart10	uart10	44, 45, 46, 47
qup1_se4 (0xa90000)	spi11	i2c11	uart11	—	48, 49, 50, 51
qup1_se5 (0xa94000)	spi12	i2c12	uart12	—	52, 53, 54, 55
qup1_se6 (0xa9c000)	—	i2c13	uart13	—	56, 57, 56, 57

QUP2 (SE0–SE6)

QUP_SE (addr)	SPI-M	I2C-M	UART	HS UART	GPIO mapping
qup2_se0 (0x880000)	spi14	i2c14	uart14	—	80, 81, 82, 83
qup2_se1 (0x884000)	spi15	i2c15	uart15	—	84, 85, 99, 100
qup2_se2 (0x888000)	spi16	i2c16	uart16	uart16	86, 87, 88, 89, 90
qup2_se3 (0x88c000)	spi17	i2c17	uart17	uart17	91, 92, 93, 94
qup2_se4 (0x890000)	spi18	i2c18	uart18	—	95, 96, 97, 98
qup2_se5 (0x894000)	spi19	i2c19	uart19	—	99, 100, 95, 96
qup2_se6 (0x898000)	spi20	i2c20	uart20	—	97, 98, 95, 96

QUP3 (SE0)

QUP_SE (addr)	SPI-M	I2C-M	UART	GPIO mapping
qup3_se0 (0xb80000)	spi21	i2c21	uart21	13, 14, 15, 16, 17, 18, 19

SPI-M = SPI Master

QUP Lane to Function Mapping

Interface	L0	L1	L2	L3	L4	L5
UART	CTS	RFR	Tx	Rx
HS UART	CTS	RFR	Tx	Rx
I2C	SDA	SCL
SPI master	MISO	MOSI	SCLK	CS_0	CS_1	CS_2

Set Up the Device Interface

Obtain Boot Logs

# SSH to device, then:
dmesg

List Enabled Interfaces

# UART
ls /dev/tty*

# I2C
ls /dev/i2c*
# Expected: /dev/i2c-18  /dev/i2c-19  /dev/i2c-20  /dev/i2c-21  /dev/i2c-22

Load QUP v3 Firmware

The Application Processor serial engines are managed by the Linux kernel. Firmware files are at:

/lib/firmware/qcom/<target-name>/qupv3fw.elf

Enable in kernel config:

CONFIG_QCOM_QUP_FW_LOAD=y   # in qcom_defconfig
CONFIG_QCOM_QUP_FW_LOAD=m   # in qcom_vm_defconfig

Device Tree Configuration

IQ-9075 EVK reference device tree: arch/arm64/boot/dts/qcom/sa8775p.dtsi

Sample Configurations

I2C
SPI
UART

i2c10: i2c@a8c000 {
  compatible = "qcom,geni-i2c";
  reg = <0x0 0xa8c000 0x0 0x4000>;
  interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
  clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
  clock-names = "se";
  pinctrl-0 = <&qup_i2c10_default>;
  pinctrl-names = "default";
  power-domains = <&rpmhpd SA8775P_CX>;
  dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
         <&gpi_dma1 1 3 QCOM_GPI_I2C>;
  dma-names = "tx", "rx";
  status = "disabled";
};

spi11: spi@a90000 {
  compatible = "qcom,geni-spi";
  reg = <0x0 0xa90000 0x0 0x4000>;
  interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
  clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
  clock-names = "se";
  pinctrl-0 = <&qup_spi11_default>;
  pinctrl-names = "default";
  power-domains = <&rpmhpd SA8775P_CX>;
  dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
         <&gpi_dma1 1 4 QCOM_GPI_SPI>;
  dma-names = "tx", "rx";
  status = "disabled";
};

uart12: serial@a94000 {
  compatible = "qcom,geni-uart";
  reg = <0x0 0x00a94000 0x0 0x4000>;
  interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
  clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
  clock-names = "se";
  pinctrl-0 = <&qup_uart12_default>;
  pinctrl-names = "default";
  power-domains = <&rpmhpd SA8775P_CX>;
  status = "disabled";
};

Device Tree Properties

Property	Type	Description	Required
`status`	string	`okay` or `disabled`	Yes
`clock-frequency`	u32	I2C clock frequency (Hz)	Optional
`spi-max-frequency`	u32	SPI max frequency (Hz)	Optional
`pinctrl-names`	string array	Pin control state names	Recommended
`pinctrl-0`	phandle	Default pin configuration	Recommended

Modify Serial Engine Node

To enable or change a serial engine, modify the device tree and rebuild the kernel.

As a first step, refer to the “How to build the linux-qcom kernel for Qualcomm platform?” section from Ubuntu Qualcomm IOT Platform Support.

Set up host machine

sudo apt update && sudo apt build-dep -y linux
sudo apt install build-essential gcc-aarch64-linux-gnu debhelper crossbuild-essential-amd64 dwarves
sudo snap install rustup --classic && rustup install stable

Identify kernel version on device

uname -a
# Example: Linux ubuntu 6.8.0-1064-qcom ...

Download and checkout kernel

git clone https://git.launchpad.net/~canonical-kernel/ubuntu/+source/linux-qcom/+git/noble
cd noble
git checkout 6.8.0-1064-qcom

Enable the interface in device tree

Device tree files for IQ-9075 EVK:

qcs9075-addons-iq-9075-evk.dts
qcs9075-iq-9075-evk.dts
sa8775p.dtsi

Example — enable UART12:

&uart12 {
    status = "okay";
};

Example — enable I2C4:

&i2c4 {
    status = "okay";
};

Build the kernel

cd noble
export ARCH=arm64
export $(dpkg-architecture -aarm64)
export CROSS_COMPILE=aarch64-linux-gnu-
fakeroot debian/rules clean
fakeroot debian/rules binary

Extract and deploy DTB

mkdir out
dpkg-deb -x linux-modules-6.8.0-1064-qcom_6.8.0-1064.65_arm64.deb ./out

scp out/lib/firmware/6.8.0-1012-qcom/device-tree/qcom/qcs9075-iq-9075-evk.dtb \
  ubuntu@<ip>:/home/ubuntu/

ssh ubuntu@<ip>
sudo mv /home/ubuntu/qcs9075-iq-9075-evk.dtb \
  /usr/lib/firmware/6.8.0-1064-qcom/device-tree/qcom/
sudo reboot

Switch Serial Engine Protocol

To convert a serial engine from one protocol to another (e.g., SPI10 → I2C10):

# In qcs9075-iq-9075-evk.dts:

# Disable SPI
&spi10 {
    status = "disabled";
};

# Enable I2C
&i2c10 {
    status = "okay";
};

Troubleshooting

# List I2C buses
ls -la /sys/bus/i2c/devices/

# List SPI buses
ls -la /sys/bus/spi/devices/

# Check UART devices
ls -la /dev/ttyHS*

# QUP-related kernel messages
dmesg | grep -i qup
dmesg | grep -i geni
dmesg | grep -i firmware

# Check compiled device tree
dtc -I fs /sys/firmware/devicetree/base | grep -A 20 qupv3

Firmware Loading Failed

Symptom: qcom-geni-se: firmware request failed

ls -la /lib/firmware/qcom/
# Verify CONFIG_FW_LOADER=y in kernel config

Serial Engine Not Probing

Symptom: No device node created; driver not loading.Verify device tree: status = "okay"; (not "ok" or "enable")

dmesg | grep -i qup
dmesg | grep -i geni

Protocol Conflict

Symptom: qcom-geni-se: serial engine is already in useEnsure only one protocol is enabled per serial engine:

# WRONG — both enabled
&qupv3_se5_i2c { status = "okay"; };
&qupv3_se5_spi { status = "okay"; };

# CORRECT — only one enabled
&qupv3_se5_i2c { status = "okay"; };
&qupv3_se5_spi { status = "disabled"; };

Enable Required Interfaces

UART — see UART software device tree configuration
SPI — see SPI software configuration
I2C — see I2C software device tree configuration
PCIe — see PCIe software driver configuration
USB — see USB configuration guide

​IQ-9075 Interface Overview

​QUP v3 Protocol and GPIO Mapping

​QUP0 (SE0–SE5)

​QUP1 (SE0–SE6)

​QUP2 (SE0–SE6)

​QUP3 (SE0)

​QUP Lane to Function Mapping

​Set Up the Device Interface

​Obtain Boot Logs

​List Enabled Interfaces

​Load QUP v3 Firmware

​Device Tree Configuration

​Sample Configurations

​Device Tree Properties

​Modify Serial Engine Node

​Switch Serial Engine Protocol

​Troubleshooting

​Enable Required Interfaces

IQ-9075 Interface Overview

QUP v3 Protocol and GPIO Mapping

QUP0 (SE0–SE5)

QUP1 (SE0–SE6)

QUP2 (SE0–SE6)

QUP3 (SE0)

QUP Lane to Function Mapping

Set Up the Device Interface

Obtain Boot Logs

List Enabled Interfaces

Load QUP v3 Firmware

Device Tree Configuration

Sample Configurations

Device Tree Properties

Modify Serial Engine Node

Switch Serial Engine Protocol

Troubleshooting

Enable Required Interfaces